1. Field of the Invention
The present invention relates to an insulated gate semiconductor device, and more particularly relates to an insulated gate semiconductor device having improved reliability by stabilizing VDSS breakdown voltage characteristics.
2. Description of the Related Art
As a conventional insulated gate semiconductor device, there has been known an insulated gate semiconductor device in which transistors performing main operations, and sensing transistors performing current detection and the like in the transistors are integrated into one chip. This technology is described for instance in Japanese Patent Application Publication No. 2002-314086.
FIG. 5 is a plan view showing a MOSFET having a trench structure, as an example of a conventional insulated gate semiconductor device. Note that metal electrode layers, such as a source electrode and a gate pad electrode, and an interlayer insulating film are not shown in FIG. 5.
As shown in FIG. 5, an operation part 41, in which MOS transistors 35m performing main operations are disposed, and a sense part 42, in which sensing MOS transistors 35s are disposed, are integrated in a MOSFET chip. Moreover, respective channel regions 33 and 34 of the operation part 41 and the sense part 42 are separated from each other at a predetermined interval.
A semiconductor substrate 30 is formed by stacking an n− type semiconductor layer on an n+ type silicon semiconductor substrate to obtain a drain region. The p type channel regions 33 and 34 are provided in a surface of the n+ type semiconductor layer. Moreover, trenches are provided in the channel regions 33 and 34, and gate electrodes are buried in the trenches after covering insides of the trenches with insulating films. The MOS transistors 35m and 35s are arranged, for example, in a lattice pattern. The MOS transistors 35m and 35s in the respective channel regions 33 and 34 have the same configuration.
The gate electrode which drives the sense part 42 is connected to the gate electrode in the operation part 41 by a gate connection electrode 36 made of polysilicon or the like. In the substrate surface, for example, at one of corner portions of the operation part 41, a gate pad electrode (not shown) is provided, which is connected to the gate connection electrode 36.
Specifically, the MOS transistors 35m and 35s in the operation part 41 and the sense part 42 are simultaneously driven, and a current is detected by the sense part 42. Thus, abnormalities such as an overcurrent in the operation part 41 are monitored and controlled.
In the conventional MOSFET, when the operation part 41 and the sense part 42 are integrated into one chip, as shown in FIG. 5, the channel regions 33 and 34 are separated from each other, and the MOS transistors 35m and 35s are formed and connected to one gate electrode.
The sense part 42 is disposed, for example, along a peripheral edge of the chip such as a corner portion of the chip. Specifically, when the sense part 42 is provided, a peripheral shape of (the channel region 33 of) the operation part 41 has at least six or more corner portions along a shape of (the channel region 34 of) the sense part 42.
In such a case, curvatures of the respective corner portions at points X1 to X6 and points Z1 to Z4 in the respective channel regions 33 and 34 are set equal in order to secure a predetermined drain-source breakdown voltage (hereinafter referred to as a VDSS breakdown voltage). Moreover, curvatures of depletion layers spreading outward from the respective channel regions 33 and 34 in application of a reverse voltage are set approximately equal.
Note that, when patterns of the points X and Z are set to be convex parts, points Y to be concave parts are an advantageous pattern for the VDSS breakdown voltage since the depletion layers sufficiently spread compared with the convex parts. In other words, curvatures of the points Y have almost no influence on the VDSS breakdown voltage. Thus, it is only necessary to give consideration to the points X and Z.
Here, for example, in the case where the operation part 41 and the sense part 42 are disposed close to each other to the extent that the depletion layer spreading from the operation part 41 and the depletion layer spreading from the sense part 42 are pinched off in a hatching region, the breakdown voltage of the chip is influenced by the curvatures at the points X1, Z2 and X4 to X6. Specifically, if the curvatures of at least the points X1, Z2 and X4 to X6 are set equal, theoretically, the depletion layers spreading outward are set approximately uniform in the entire chip. Thus, a decrease in the breakdown voltage is prevented.
The transistors in the operation part 41 and the sense part 42 have the same configuration. When measurements are made in the operation part 41 and the sense part 42 as discrete chips shown in FIG. 5, gate-source voltages and drain-source voltages, which are applied to the respective parts, are the same.
However, in an actual application, for example, a current detection resistance outside the chip is connected only to the sense part 42, and a current in the operation part 41 is detected by a control IC. Thus, the applied gate-source voltages and drain-source voltages differ between the operation part 41 and the sense part 42.
Accordingly, for example, even if the curvatures of the point X1 in the channel region 33 and the point Z2 in the channel region 34 are equal, the drain-source voltages applied to the operation part 41 and the sense part 42 are different from each other. This causes a variation in the depletion layers spreading at the points X1 and Z2, and produces a problem of a variation in the VDSS breakdown voltage.
Meanwhile, in the case where the operation part 41 and the sense part 42 are disposed so as to be separated from each other to the extent that the depletion layers spreading from the operation part 41 and the sense part 42 are not pinched off in application of the reverse voltage in the hatching region, the curvatures of the points X1 to X6 and Z1 to Z4 to be the respective corner portions are all set equal. Consequently, a stable VDSS breakdown voltage can be obtained in the entire chip.
However, in the above case, it is necessary to provide a sufficient space between the operation part 41 and the sense part 42 (the hatching region) and to sufficiently reduce the curvature so as to obtain a predetermined breakdown voltage at each of the corner portions. For this reason, there is a problem that arrangement areas (the number of cells) of the MOS transistors 35m and 35s are reduced.